MK2069-04GILFTR【PDF 4/20 页】IC VCXO CLK TRANSLATOR 56-TSSOP

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MK2069-04

VCXO-BASED UNIVERSAL CLOCK TRANSLATOR

VCXO AND SYNTHESIZER

IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR

MK2069-04

REV J 051310

There should be no signal traces near the crystal or the

traces. Also refer to the Optional Crystal Shielding section

that follows.

4) To minimize EMI the 33

Ω series termination resistor, if

needed, should be placed close to the clock output.

5) All components should be on the same side of the board,

minimizing vias through other signal layers (the ferrite bead

and bulk decoupling capacitor may be mounted on the

back). Other signal traces should be routed away from the

MK2069-04. This includes signal traces on PCB traces just

underneath the device, or on layers adjacent to the ground

plane layer used by the device.

6) Because each input selection pin includes an internal

pull-up device, those inputs requiring a logic high state (“1”)

can be left unconnected. The pins requiring a logic low state

(“0”) can be grounded.

Optional Crystal Shielding

The crystal and connection traces to pins X1 and X2 are

sensitive to noise pickup. In applications that especially

sensitive to noise, such as SONET or G-Bit ethernet

transceivers, some or all of the following crystal shielding

techniques should be considered. This is especially

important when the MK2069-04 is placed near high speed

logic or signal traces.

The following techniques are illustrated on the

Recommended PCB Layout drawing.

1) The metal layer underneath the crystal section should be

the ground layer. Remove all other layers that are above.

This ground layer will help shield the crystal circuit from

other system noise sources. As an alternative, all layers

underneath the crystal can be removed, however this is not

recommended if there are adjacent PCBs that can induce

noise into the unshielded crystal circuit.

2) Cut a channel in the PCB ground plane around the crystal

area as shown. This will eliminate high frequency ground

currents that can couple into to crystal circuit.

3) Add a through-hole for the optional third lead offered by

the crystal manufacturer (case ground). The requirement for

this third lead can be made at prototype evaluation. The

crystal is less sensitive to system noise interference when

the case is grounded.

4) Add a ground trace around the crystal circuit to shield

from other active traces on the component layer.

The external crystal is particularly sensitive to other system

clock sources that are at or near the crystal frequency since

it will try to lock to the interfering clock source. The crystal

should be keep away from these clock sources.

The IDT Applications Note MAN05 may also be referenced

for additional suggestions on layout of the crystal section.

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